SESSION F Tuesday, 30 September
Radiation Hardening Techniques
Chairs: Ying Cao & Laurent Berti
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Queen Elisabeth Hall
F1 15:20 - 15:35
All-Digital Phase-Locked Loop with Single-Event Phase and Frequency Transient Suppression​
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Authors: S. Biereigel(1), S. Kulis(1), P. Moreira(1)
1. CERN, Switzerland
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Presenting author: Stefan Biereigel
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Improvement of radiation tolerance of an all-digital bang-bang PLL circuit using an auxilliary TDC circuit. The TDC allows detecting and reacting to larger phase deviations by the loop with low power overhead.
F2 15:35 - 15:50
Self-Correcting Flip-flop Circuit Avoiding Soft Error Accumulation in Low Power Designs
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Authors: A. Jain(1), A. Veggetti(2), D. Crippa(3), A. Benfante(4), A. Sharma(1)
1. STMicroelectronics, India, 2. STmicroelectronics, Italy, 3. STMircoelectronics, Italy, 4. STMicroelectronics, Italy
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Presenting author: Abhishek Jain
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A novel flip-flop architecture is presented which can load data asynchronously on assertion of enable signal, it can be implemented in DMR or TMR configuration with error detection to provide immunity to soft error.
F3 15:50 - 16:05
ML/AI-Based SEL/µ-SEL Detection in a COTS System without Modifying the COTS System​
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Authors: J. Zhao(1), Y. Sun(1), T. Zhang(2), K. Chong(2), W. Shu(2), J. Chang(1)
1. NTU, Singapore, 2. Zero-Error Systems (ZES) Pte Ltd, Singapore
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Presenting author: Junkai Zhao
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We propose an adaptive pre-processing module for ML/AI-based approaches to enhance the detection of SELs/µ-SELs in a COTS system (embodying multiple COTS ICs) by monitoring only its input power rail, without modifying the COTS system.
F4 16:05 - 16:20
Self-Healing Gate-Controlled LPNP Device Using Electrical Annealing to Mitigate TID Radaition-Induced Degradation​
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Authors: W. Ma(1), Z. Wang(2), X. Ouyang(1)
1. Northwest Institution of Nuclear Technology, China, 2. Chongqing Yuxin Electronics Co., Ltd., China
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Presenting author: Wuying Ma
​​Radiation-hardened bipolar transistor with oxide-embedded polysilicon microheater achieves 96% recovery in 60s via Joule heating, mitigating 40 krad(Si) TID damage while preserving electrical characteristics and enabling in situ real-time defect annealing for space radiation environments.
POSTERS
PF-1
A Timing-Slack-Driven Hardening Method for Single-Event Effects Mitigation Without Circuit Performance Degradation​
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Authors: R. Song(1), C. Hu(1), J. Shao(1), Y. Chi(1), B. Liu(1), B. Liang(1), J. Chen(1), Z. Wu(1)
1. National University of Defense Technology, China
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Presenting author: Ruiqiang Song
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The proposed method replaces commercial flip-flops with hardened flip-flops or inserts filter instances based on timing slack values. Experimental results demonstrate that the proposed method enhances tolerance to single-event effects without degrading circuit performance.
PF-2
Enhancing SEL Immunity in Commercial Technology for Aerospace Applications through Process-Based Solutions​
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Authors: L. Montagner(1), D. Truyen(2), J. Wong(3), E. Leduc(2)
1. Microchip Technology Rousset, France, 2. Microchip Technology, France, 3. Microchip Technology, USA
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Presenting author: Laurence Montagner
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We developed a method to harden 0.18µm commercial technology against SEL for aerospace applications. TCAD simulations guided process-based solutions, implemented and validated through heavy-ion testing on test vehicles, confirming the complete elimination of SEL vulnerabilities.
PF-3
Hardened Logic Cells Against Soft Errors with 3.75x10^{-8} cm^{2} Cross-section for Combinational Circuits in 28nm CMOS Process​
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Authors: Y. Li(1), C. Chen(2), J. Zhang(1), B. Zhang(1), F. Lang(1), Y. Hu(1), W. Zhan(3), X. Zeng(1)
1. State Key Laboratory of Integrated Chips and Systems, Fudan University, China, 2. State Key Laboratory of Integrated Chips and Systems, Fudan University, China, 3. Anqing Normal University, China
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Presenting author: Yan Li
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This paper proposes SFOL, a low-cost hardening technique for combinational cells that filters transients and suppresses SETs. Fabricated in 28nm CMOS, SFOL reduces SET pulses by 96% and cross-section by 4x compared to standard cells.
PF-4
Irradiation Hardening of p-GaN HEMT Based on AlN Polarization Regulation Mechanism
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Authors: W. Fan(1), J. Qiu(2), W. Huang(3), J. Shen(2), D. Zhang(1)
1. Fudan University, China, 2. China Resources Microelectronics (Chongqing) Limited, China, 3. Jiangnan University, China
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Presenting author: Wenqi Fan
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AlN polarization in post-irradiation HEMT can enhance the GaN layer charge sharing and suppress DIBL effect. Gate carrier transport model is proposed to reveal that AlN reduces irradiated traps and has an effective irradiation-hardening ability.
PF-5
Leveraging Tap Cell as a Soft Error Mitigation Method for Advanced CMOS Combinational Circuits without Additional Area Overhead​
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Authors: C. Zhang(1), C. Chen(2), F. He(1), H. Yin(1), Y. Li(1), X. Zeng(1)
1. State Key Laboratory of Integrated Chips and Systems, Fudan University, China, 2. State Key Laboratory of Integrated Chips and Systems, Fudan University, China
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Presenting author: Chenyu Zhang
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This paper proposes a layout-level tap cell placement method to mitigate SET in combinational circuits, achieving 5–11% SER reduction with no area overhead and minimal power and delay impact.