SESSION B Tuesday, 30 September
Single Event Effects: Devices & ICs
Chairs: Magali Haussy & Enxia Zhang
Queen Elisabeth Hall
B1 09:05 - 09:20
Comparing SEU Vulnerability of SRAM and D-FF Cells in a 3-nm FinFET Technology
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Authors: N. Pieper(1), Y. Xiong(1), J. Kronenberg(1), D. Ball(1), B. Bhuva(1)
1. Vanderbilt University, USA
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Presenting author: Nicholas Pieper
Numerous factors are shown to strongly affect single-event upset (SEU) vulnerability for storage cells, resulting in Flip-Flop cells having greater vulnerability than SRAM cells at a 3-nm FinFET technology.
B2 09:20 - 09:35
Effects of Temperature and Supply Voltage of the SE Cross-Sections for Flip-flop Designs at 7-, 5-, and 3-nm bulk FinFET Nodes
Authors: X. Zhao(1), J. Kronenberg(1), Y. Xiong(1), N. Pieper(1), S. Ball(1), B. Bhuva(1)
1. Vanderbilt University, USA
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Presenting Author: Xiaotong Zhao
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SE cross-sections of D flip-flops at 7-nm, 5-nm, and 3-nm FinFET nodes are investigated at elevated temperatures across a range of supply voltages.
B3 09:35 - 09:50
Improvement of Heavy Ion-Induced Single-Event Burnout Tolerance Based on Automotive SiC Trench MOSFETs
Authors: E. Kagoshima(1), M. Takahashi(2), M. Iwata(2), T. Suzuki(2), R. Kihara(1), T. Nishiwaki(1), H. Fujiwara(1), H. Shindou(2) ​1. MIRISE Technologies, Japan, 2. Japan Aerospace Exploration Agency, Japan
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Presenting Author: Eiji Kagoshima
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Single-event burnout (SEB) tolerance was improved in SiC trench MOSFETs by applying double or triple drift layers. It was confirmed experimentally that this multi-drift layer technique resolved the trade-off between SEB tolerance and on-resistance.
B4 09:50 - 10:05
Comparison of Heavy-Ion and Laser-Induced Single-Event Frequency Transients in CMOS LC-Tank Oscillators.
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Authors: G. Adom-bamfi(1), Q. Ma(1), S. Biereigel(2), P. Leroux(1), J. Prinzie(1)
1. KU Leuven, Belgium, 2. CERN, Switzerland
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Presenting author: Gideon Adom-Bamfi
This paper analyzes Single-Event Frequency Transients in CMOS LC-tank oscillators using heavy ions and 1064 nm pulsed laser testing, validating laser testing as an effective method for emulating radiation effects in inductors.
B5 10:05 - 10:20
Back-Gate Bias Suppression of High-Temperature Enhanced SEU Sensitivity in the DSOI Technology
Authors: Y. Sun(1), Y. Wang(1), S. Chen(2), F. Liu(1), L. Wang(1), B. Li(1), J. Gao(1), C. Wang(1), G. Zhang(1), K. Wang(1), L. Shu(1), L. Wang(1), T. Ye(1)
1. Institute of Microelectronics, Chinese Academy of Sciences, China, 2. institute of microelectronics of the chinese academy of sciences, China
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Presenting Author: Yuxin Sun
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The single-event upset (SEU) cross-section is experimentally shown to increase with temperature due to significant single-event transient pulse broadening and SRAM cell stability degradation. A negative back-gate bias applied to NMOS suppresses temperature-enhanced SEU sensitivity.
B6 11:00 - 11:15
Quasi Event-Wise Measurement of Neutron-Induced Multiple-Cell Upsets in 22-nm and 55-nm SRAMs
Authors: Y. Gomi(1), K. Takami(1), R. Yasuda(1), H. Kanda(2), M. Fukuda(2), M. Hashimoto(1)
1. Kyoto univ., Japan, 2. Osaka univ., Japan
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Presenting Author: Yuibi Gomi
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We measured neutron‑induced SEUs, including Distant MCUs, in dedicated self‑scan 22/55-nm SRAMs, finding that Distant MCUs account for 13% of MCUs. We also evaluated conventional bitmap‑based methods, showing narrow grouping distances prevent Distant MCU characterization.
B7 11:15 - 11:30
Observation of Higher Upset Rates in Multi-Bit Flip-Flops Utilized in Low Power Designs
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Authors: J. Kim(1), R. Bloom(1), Y. Yi(1), C. Lim(2), I. Jang(2), J. Jin(2), Y. Hwang(2), K. Chun(2), C. Kim(1)
1. University of Minnesota, USA, 2. Samsung Electronics Co., Ltd, Korea, Republic of
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Presenting Author: Junkyu Kim
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Neutron-induced upset results for multi-bit flip-flops with standard and DICE latch structures are presented. We uncover new vulnerabilities of multi-bit flip-flops, a popular technique for reducing chip power consumption, stemming from the shared clock buffer.
POSTERS
PB-1
Effect of Temperature on the SEU Cross-Section in a 40-nm SRAM when Exposed to Low-Energy Protons
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Authors: P. Martin Holgado, A. Romero Maestre, J. De Martin Hernandez, Y. Morilla Centro Nacional de Aceleradores (CNA), Spain
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Presenting author: Pedro Martin Holgado
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This work explores the impact of temperature on the SEU cross-sections of a 40-nm SRAM under low-energy proton irradiation. Tests in the PHOENIX chamber show slight temperature-dependent variations with a minimum sensitivity at 0 ºC.
PB-2
Investigation of Neutron-Induced Failures in Commercial SiC Power Devices
Authors: N. Arnold(1), V. Kotagama(1), G. Parkinson(2), K. Niskanen(3), A. Renz(1), P. Gammon(1)
1. University of Warwick, United Kingdom, 2. University of Nottingham, United Kingdom, 3. University of Jyväskylä, Finland
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Presenting Author: Niamh Arnold
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Accelerated neutron testing was completed on a range of current-market SiC commercial devices in the 650 V and 1.2 kV range, resulting in an appraisal of cosmic ray resilience performance in current market devices.
PB-3
Single Event Transient Evaluation of 7nm FinFET LUT4 Representative of Versal
Authors: A. Urena-acuna(1), L. Artola(1), G. Hubert(1), S. Achaq(2), V. Pouget(3), J. Boch(4), F. Manni(5)
1. ONERA, France, 2. ONERA/IES, France, 3. IES-CNRS, France, 4. Univ Montpellier, France, 5. CNES, France
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Presenting Author: Alejandro Urena-Acuna
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In this work, we present an evaluation methodology to determine the SET sensitivity through a heavy ion simulated fault injection technique on a LUT4 of the 7nm FinFET AMD Xilinx Versal FPGA
PB-4 withdrawn
Deep Underground Experiment and Simulation of Soft Error Characteristics in 14 nm FinFET and 28 nm SRAMs
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Authors: Y. Dong(1), Z. Zhang(2), G. Lu(1)
1. China Electronic Product Reliability and Environmental Testing Research Institute,, China, 2. China Electronic Product Reliability and Environmental Testing Research Institute, China
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Presenting author: Zhangang Zhang
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Underground SER testing of 14/28nm SRAMs at CJPL recorded 16 errors (18.6% MCUs,max 7 cells) over 862 days. Hard/fake errors observed. High-altitude comparisons reveal Beijing SER trends. Monte Carlo simulations validate alpha-induced charge mechanisms.
PB-5
Investigation on SET Pulse Width Changes in Combinational Logic Circuits by Fault Injections
Authors: T. Yuta(1), T. Nakura(2) ​
1. Japan Aerospace Exploration Agency, Japan, 2. Fukuoka University, Japan
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Presenting Author: Tsuchiya Yuta
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We propose a measurement-based technique to investigate changes in Single-Event Transient pulse width caused by pulse propagation effects. The pulse width broadening is comparable to the original SET pulse width at the ion hit position.
PB-6
Static and Dynamic Tests on a 40-nm Commercial SRAM under Muons and Neutrons
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Authors: J. Fabero(1), F. Franco(1), H. Mecha(1), M. Rezaei(1), A. Hillier(2), J. Lord(2), S. Cottrell(2), A. Colangeli(3), N. Funnesu(3), G. Pagano(3),
J. Clemente(1)
1. Universidad Complutense de Madrid, Spain, 2. STFC Rutherford Appleton Laboratory, United Kingdom, 3. ENEA, Italy
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Presenting Author: Francisco J Franco
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The SBU and MCU cross sections for muons and 14-MeV neutrons of a commercial 40-nm CMOS SRAM were experimentally determined in static and dynamic modes. Events are more likely in static mode than in dynamic mode.
PB-7 withdrawn
Investigation of Single-Event Effects Induced by Heavy Ion Irradiation on GaN MMIC Power Amplifiers
Authors: H. Zhang, X. Jian, W. Xiaoqiang, L. Hongwei, T. Rui, J. Xing, W. Bin
China Electronic Product Reliability and Environmental Testing Research Institute, China
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Presenting Author: Hao Zhang
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This study investigates single-event effects in GaN MMIC power amplifiers, revealing significant performance degradation and single-event burnout in HEMTs and MIM capacitors. Mechanisms include electron trapping and dielectric rupture, confirmed by SEM and simulations.
PB-8
Single Event Effects of Power Bipolar Junction transistors
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Authors: JF. Faillace, V. Gupta, B. Thomas, M. Muschitiello, A. Costantino, F. Krimmel, P. Hernandez, P. Heiskanen, F. Tonicello
European Space Agency, Netherlands​
Presenting Author: Francesco Faillace
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This work investigates the Single Event Effects radiation hardness level of power Bipolar Junction Transistors, with a main focus on Single Event Burnout. Several COTS devices were tested with heavy ions for SEE characterization.
PB-9L
Heavy Ion Induced Single Event Effects in 6.5 kV and 10 kV SiC Power MOSFETs and Comparison to the Depletion Capacitance Energy Model
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Authors: S. Islam(1), A. Sengupta(1), D. Ball(1), J. Osheroff(2), K. Galloway(3), A. Witulski(1), S. Kosier(1), R. Schrimpf(1)
1. Vanderbilt University, USA, 2. NASA Goddard Space Flight Center, USA, 3. Vanderbilt university, USA
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Presenting Author: Sajal Islam
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Heavy ion irradiation of 6.5 kV and 10 kV SiC MOSFETs shows agreement with the depletion capacitance critical energy model. Leakage and failure regions are identified, extending the model’s relevance to high-voltage SiC power devices.
PB-10L
Cumulative and Transient Effects in SELC II of Planar and Trench-Gate SiC Power MOSFETs
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Authors: N. Für(1), H. Medeiros(1), M. Belanche guadas(1), A. Erlebach(1), M. Nagel(2), U. Grossner(3)
1. APS - ETH Zürich, Switzerland, 2. APS - ETH Zurch, Switzerland, 3. APS - ETH Zurich, Switzerland
Presenting Author: Natalija Für
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Degradation in planar and trench-gate silicon carbide (SiC) power MOSFETs induced by heavy-ion irradiation (SELC II and SEB) has been further characterized and cumulative and transient behavior observed.